Athlon XP, Bridge configurations

The following reports are applicable in Barton and Thoroughbred including Thorton and Applebred.
The corresponding product is Athlon XP, Sempron, and Duron. However, the content of this page is not necessarily certain. Please confirm it by yourself. These contents require the knowledge of Electronic parts.

Function of the bridge for the desktop CPUs.

Bridge number

  • L1 : It is connected from L3 to BP_FID pin.
  • L2,L9 : Level2 Cache controls
  • L3 : Start up Multipliers
  • L5 : Operation mode of CPU
  • L6 : SFID, Rated Multiplier for Mobile
  • L8 : SVID, Maximum Core voltage for Mobile
  • L11 : VID, Start up Core voltage
  • L12 : FSB auto-detection
  • Summary : About closing of the bridges

L1 : It is connected from L3 to BP_FID pin.

L1 bridge(Electronic point of contact) has connected between L3 and BP_FID Pin. Therefore, in order to change the Multiplier from the Motherboard, it is required for the whole of L1 to have closed.



L2 : Level2 Cache controls

Although L2 bridge controls Level2 Cache size, the state where all are closed is a default.

All L9 is opened. However, this bridge is not related to recognition of L2.
However, this bridge is required when controlling L2-Cache from the outside of CPU.


L2 Bridges
OPNL2[3:0]L2 CacheProducts
AXDA1700DLT3CCCCC256k
T-bred CORE		Athlon XP
AXMH2200FQQ3CAthlon XP-M
SDA2400DUT3DSempron
ANXS1750FXC3SGeode NX
AXDA2500DKV4DCCCC512k
Barton CORE		Athlon XP
AXMG2600FQQ4CAthlon XP-M
SDA3000DUT4DSempron

T-bred* = Thoroughbred

Thorton [ AMD athlon Processor Model 10 w/256K L2 Cache ]

The Thorton is using the Barton core. We think that this bridge setup is a decisive difference with Barton.

Athlon Thorton L2 bridges
OPNL2[3:0]L2 CacheDevelopment code
AXDC2400DKV3C
AQXEA 0337TPMW 9738095270198		CCC:256kThorton
AXDC2000DUT3C
AQXCA 0321MPMW 9871266270062		CC:C256kThorton


Applebred [ AMD Duron Processor Model 8 w/64K L2 Cache ]

The new Duron called Applebred is using the Thoroughbred core. Though it is the same core as Athlon, it is Duron because L2 [3] is open. Just this bridge setup considers us to be the decisive differences from Thoroughbred.

Duron Applebred L2 bridges
OPNL2[3:0]L2 CacheDevelopment code
DHD1600DLV1C
MIXHB 0333VPMW Z321435240056		:CC:64kApplebred
DHD1600DLV1C
MIXHB 0333UPMW Z321075260221		:CCC64kApplebred

: = Open (Level:H)
C = Closed (Level:L)


Though all these bridges are closed, L2 Cache does not necessarily operate correctly.
We recommend you to perform the Torture-test of Prime95

I think that L3[1] and L3[0] will become selection of the invalid area of L2 Cache.

This bridge seems to be the same function as Palomino. Please refer to the following page.
Palomino/L2 details


L3 : SYSCLK Multiplier

Caution : In the super-locked Athlon XP and Sempron, the multiplier doesn't change even if you change these bridges.

It is the important bridge which sets up the Multiplier of Athlon XP.

AXDA3000DKV4D
  • Close L3-FID 4 : 5X to 12.5X
  • Open L3-FID 4 : Over13X

On this page, Multiplier bridges are written to be L3-FID bridges.


Barton FSB:167

MultiplierClock
(FSB167)		L3-FID[4:0]Model#
5.0x 833CC:CC -
5.5x 917CC:C: -
6.0x1000CC::C -
6.5x1083CC::: -
7.0x1167C:CCC -
7.5x1250C:CC: -
8.0x1333C:C:C -
8.5x1417C:C:: -
9.0x1500C::CC -
9.5x1583C::C: -
10.0x1667C:::C -
10.5x1750
2100		C:::: -
*3000+
11.0x1833
2200		CCCCC2500+
*3200+
11.5x1917CCCC:2600+
12.0x2000CCC:C -
12.5x2083CCC::2800+
MultiplierClock
(FSB167)		L3-FID[4:0]Model#
13.0x2167:C:CC3000+
13.5x2250:C:C: -
14.0x2333:C::C -
21.0x - :C::: -
15.0x2500::CCC -
22.0x - ::CC: -
16.0x2667::C:C -
16.5x2750::C:: -
17.0x2833:::CC -
18.0x3000:::C: -
23.0x - ::::C -
24.0x -
- 		::::: -
n/aInvalid:CCCC -
-
19.0x - :CCC: -
n/aInvalid:CC:C -
20.0x - :CC:: -

C = Closed , : = Open , * = FSB:200


Thoroughbred FSB:133

MultiplierClock
(FSB133)		L3[4:0]Model#
5.0x 667MCC:CCM_100*
5.5x 733MCC:C: -
6.0x 800MCC::CM_133*
6.5x 867MCC::: -
7.0x 933MC:CCC -
7.5x1.00GC:CC: -
8.0x1.07GC:C:C -
8.5x1.13GC:C:: -
9.0x1.20GC::CC -
9.5x1.27GC::C: -
10.0x1.33GC:::C -
10.5x1.40GC:::: -
11.0x1.47GCCCCC1700+
11.5x1.53GCCCC:1800+
12.0x1.60GCCC:C1900+
12.5x1.67GCCC::2000+
MultiplierClock
(FSB133)		L3[4:0]Model#
13.0x1.73G:C:CC2100+
13.5x1.80G:C:C:2200+
14.0x1.87G:C::C -
21.0x - :C::: -
15.0x2.00G::CCC2400+
22.0x - ::CC: -
16.0x2.13G::C:C2600+
16.5x2.20G::C:: -
17.0x2.27G:::CC -
18.0x2.40G:::C: -
23.0x - ::::C -
24.0x - ::::: -
n/aInvalid:CCCC -
19.0x - :CCC: -
n/aInvalid:CC:C -
20.0x - :CC:: -

C = Closed , : = Open ,
M_100* = Mobile Athlon XP-M FSB100
M_133* = Mobile Athlon XP-M FSB133


L5 : Operation mode of CPU

XP, MP, Mobile .... It is decided by this bridge to which product it will belong. Therefore, it may be more suitable to call it "Product ID."


L5 [ 3 ] Closing : Multiprocessing Capable
L5 [ 2 ] Closing : Mobile-mode
L5 [ 1 ] Opened : default ( Valid L6 value )
L5 [ 0 ] Closed : default ( Valid L8 value )


Operation mode of CPU
OPNL5BrandProducts
[3][2][1][0]
ANXS1750FXC3SCC:CGeode NXNX 1750 (T-bred)
ANXL1500FGC3SNX 1500 (T-bred)
AXMS1400FWS3BCC:CAthlon XP-MXP-M 1400+ (T-bred)
AXMH2500FQQ4CXP-M2500+ (Barton)
AMSN2200DKT3CC::CAthlon MPMP 2200+ (T-bred)
AMSN2800DUT4CMP2800+ (Barton)
SDA2400DUT3DC::CSempronSempron 2400+ (T-bred)
SDA3000DUT4DSempron 3000+ (Barton)
AXDA1700DLT3C:::CAthlon XPXP 1700+ (T-bred)
AXDC2400DKV3CXP2400+ (Thoton)
AXDA2500DKV4DXP2500+ (Barton)
AXDA3200DKV4EXP3200+ (Barton)
DHD1600DLV1C:::CDuronDuron 1600 (Applebred)

OPN: Ordering part numbers

In a surprising thing ..... It is that operation will be continued even if it changes the state of these bridges during operation of CPU. The changes and its reverse changes to Mobile from Desktop are also possible. These were checked by T-Bred1700+ on K7S5A. However, it is thought that it does not operate well depending on BIOS or a vender.


L6 : FID for Mobile

L6 bridges are not used in CPU of the desktop version. They are all closed.
In the motherboard corresponding to mobile CPU, L6 bridge serves as multiplier rating.
Refer to the L6 bridges for PowerNow!.


MulFrequencyL6[4:0]Model#
FSB133FSB167
5.0x 667 833CC:CCANXL1250FYC3S
5.5x 733 917CC:C: -
6.0x 8001000CC::C -
6.5x 8671083CC::: -
7.0x 9331167C:CCC -
7.5x10001250C:CC:ANXL1500FGC3S
8.0x10671333C:C:C -
8.5x11331417C:C:: -
9.0x12001500C::CC -
9.5x12671583C::C: -
10.0x13331667C:::C -
10.5x14001750C::::ANXS1750FXC3S
11.0x14671833CCCCCXP, Sempron
11.5x15331917CCCC:AXMD1800FVQ3C
12.0x16002000CCC:CAXMH1900FLQ3C
12.5x16672083CCC::AXMH2000FQQ3C
MulFrequencyL6[4:0]Model#
FSB133FSB167
13.0x17332167:C:CC -
13.5x18002250:C:C:AXMH2400FQQ4C
14.0x18672333:C::CAXMH2500FQQ4C
21.0x - - :C::: -
15.0x20002500::CCCAXMG2600FQQ4C
22.0x - - ::CC: -
16.0x21332667::C:C -
16.5x22002750::C:: -
17.0x22672833:::CC -
18.0x24003000:::C: -
23.0x - - ::::C -
24.0x - - ::::: -
3.0x 400 500 :CCCC n/a
19.0x - - :CCC: -
4.0x 533 667 :CC:C n/a
20.0x - - :CC:: -

The column of FSB 333 is a reference value. It is not ratings.


L8 : SOFT VID for Mobile

L8 bridges are not used in CPU of the desktop version. They are all closed.
In CPU of the mobile version, L8 bridgs are the same setup as L11 bridges. Probably they should be used by PowerNow!.


L11 : Code to CORE Voltage Definition

CORE Voltage is decided by this bridge. However, the definitions differ in CPU of the desktop version and the mobile version.

OPNL11[4:0]Products[Thoroughbred]V_CORE
AXDA1900DLT3CC:::CAthlon XP1900+1.50V
AXDA2200DKV3CC:CCCAthlon XP2200+1.65V
AXMS1400FWS3BC:::CMobile Athlon XP1400+1.30V
AXMD1600FQQ3BC:C::Mobile Athlon XP1600+1.45V

Athlon VID Code 1
VIDVCC_CORE (V)
[4:0]DesktopMobile
CCCCC1.8502.000
CCCC:1.8251.950
CCC:C1.800(N)1.900
CCC::1.7751.850
CC:CC1.750(M)1.800
CC:C:1.7251.750
CC::C1.700(P)1.700
CC:::1.6751.650
C:CCC1.650(K)1.600
C:CC:1.6251.550
C:C:C1.600(U)1.500(L)
C:C::1.5751.450(Q)
C::CC1.550(H)1.400(V)
C::C:1.5251.350(J)
C:::C1.500(L)1.300(W)
C::::1.475 -
Athlon VID Code 2
VIDVCC_CORE (V)
[4:0]DesktopMobile
:CCCC1.4501.275
:CCC:1.4251.250(X)
:CC:C1.4001.225
:CC::1.3751.200(T)
:C:CC1.3501.175
:C:C:1.3251.150(C)
:C::C1.3001.125
:C:::1.2751.100(Y)
::CCC1.2501.075
::CC:1.2251.050
::C:C1.2001.025
::C::1.1751.000
:::CC1.1500.975
:::C:1.1250.950
::::C1.1000.925
:::::--


C = closed ( logic level of 0 ) , : = open ( logic level of 1 )

In general motherboard, even when you are using the Mobile Athlon, the voltage supplied to CPU always becomes the value of the "Desktop".


L12 : FSB auto-sensing

These bridges specify FSB Clock of rating to the motherboard.
However, a motherboard does not necessarily use the value. Since the FSB Clock can be set up manually, these bridges do not need to be changed of the usual motherboard.


L12 [ 3 ] : Closed ( default )
L12 [ 2 ] : FSB_Sense 1
L12 [ 1 ] : Closed ( default )
L12 [ 0 ] : FSB_Sense 0


L12 FSB_Sense[1:0]
OPNL12[2]L12[0]FSB Note
AXMD1600FQQ3B::100 MHzXP-M (T-bred)
AXDA1700DLT3C::133 MHzXP (T-bred)
AXDC2400DKV3CXP (Thorton)
DHD1600DLV1CDuron (Applebred)
ANXS1750FXC3S:C133 MHzGeode NX (T-bred)
ANXL1500FGC3S
AXMH2000FLQ3C:C133 MHzXP-M (T-bred)
AXMH2500FQQ4CXP-M (Barton)
AXDA2500DKV4DC:167 MHzXP (Barton)
SDA3000DDUT4DC:167 MHzSempron (Barton),
AXDA3200DKV4ECC200 MHzXP (Barton)

C = closed ( logic level of 0 ) , : = open ( logic level of 1 )

PC3200 memory is required when setting the FSB clock to 200.
PC2700 memory is required when setting the FSB clock to 167.



Attention : About closing of the bridges

Fundamentally, since processing of the bridge is dangerous, we cannot recommend you.
However, when you need processing of the bridges, be careful of below.

How to set the bridge of [Open] to [Close]
We know the Laser pit should be filled with an insulator before anything else. Then, it is made to [Close] by using electric conductive material.
In the new package(#27648), it might be difficult to connect two points in the bridge. In this case, it can be solved by filling the laser pit directly with the electric conductive material.
How to set the bridge of [Close] to [Open]
The bridge is set to [Open] by cutting carefully with an edged tool.
L bridgesAthlon XP, Sempron, Method of closing the bridges
L#FunctionImpedance
to GND		closing
+ Insulation		Closing
Directly		Notes
NewOldOld & New
L1It is connected from L3 to BP_FID pin. Insulated---Please maintain this state.
L2Level2 Cache controls1k OhmNon-recommendation
(see notes)		No Goodnotes : The behavior of the L2 Cache might be not correct.
It may be invalid in the Locked Athlon.
L3Start up Multiplier1k OhmBest
(Difficult)		OptimalGood
(see notes)		notes : It becomes impossible to use the multiplier change function of the motherboard.
Invalid in the Locked Athlon.
L5Operation mode of CPU 0 Ohm - - OptimalNo problem
L6FID, Rated Multiplier for Mobile0 Ohm - - OptimalOnly in Mobile CPU, recognition becomes possible.
L8SOFT VID, Maximum core voltage for Mobile0 Ohm - - OptimalOnly in Mobile CPU, recognition becomes possible.
L9It is connected from L2 to L2_control pinInsulatedUnnecessaryOptimalNo GoodThere is no advantage usually.
It may be invalid in the Locked Athlon.
L11VID, Start up core voltage0 Ohm - - OptimalNo problem
L12FSB auto-detection1k OhmBest
(Difficult)		OptimalGood
(see notes)		notes : It is unnecessary in a lot of mother boards.
It may be invalid in the locked Duron

The "Old,New" show a respectively new package(left) and an old package(right).

Applebred Thoroughbred
  • 11/27/2003 L12: Updated.
  • 12/15/2003 L12: AXMH2500FQQ4C is added.
  • 01/07/2004 About closing of the bridges: Updated.

Copyright 2002 ita. All rights reserved. Never reproduce or republicate without written permission.